Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavioral descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design of a layout and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product.
SPICE is a common type of simulator that is used to simulate and verify the operation of an electronic design. With SPICE, the electronic design is converted into a system of equation(s), which is then solved for a given set of inputs to check the state of specific portions of the circuit at given points in time. For many circuit designs, this process can be a very computationally expensive and time-consuming effort, especially given the size and complexity of modern circuit designs.
Conventional approaches for simulations, especially for board level simulations (e.g., simulations performed on an electronic system including the printed circuit board or PCB, one or more integrated circuit (IC) chips, and IC packaging thereof) often extract a static simulation view from the finished layout by identifying a corresponding schematic symbol from the schematic symbol library for each of a plurality of layout circuit devices. As a result, these simulation views are often termed layout extracted views or simply extracted views. The electronic design may then undergo multiple rounds of changes to the schematic, the layout, or both the schematic and the layout after the initial simulation has been performed with a simulation view extracted from the initial layout.
When these changes occur at the schematic level, these conventional approaches require a designer to implement the changes in the schematic of the electronic design, push these schematic changes to create an updated layout with a layout editor, and then extract an updated simulation view with the updated layout. The simulator may then perform another round of simulation with the updated simulation view. This loop not only requires much more time and computational resources but also presents multiple other problems.
For example, modern electronic design may include devices having distributed pins, vector pins, etc. that may be represented as an input pin in the schematic symbol. During a simulation of, for example, an electronic design with a distributed Vcc having multiple Vcc pins for a distributed power network, this distributed Vcc may be schematically represented as a single Vcc pin in the corresponding schematic symbol. In this example, if the simulation result for the Vcc shows abnormal behavior the designer will need to guess which Vcc pin or Vcc pins are causing the abnormal behavior or perform some trial-and-error changes to identify the true cause of the abnormal behavior. Similar problems and hence challenges also arise for vector pins which may be even more difficult to troubleshoot and identify the root source of any abnormal behavior simulation result due to the multiplicity of the pins.
Another problem with these conventional approaches is that the extracted view from a layout is a static view. These simulation views are generated by traversing a layout to identify layout component designs and devices, identify a corresponding schematic symbol for each of the layout component designs, place the schematic symbol in the simulation view, and interconnect the schematic symbols by referencing the layout connectivity. Although these simulation views may in some cases appear to be identical or substantially similar to the original schematic from which the layout is generated, these simulation views or extracted views may not be editable as the original schematic. As a result, any changes at the schematic level must go through the aforementioned schematic edit, layout edit, and re-extraction.
Moreover, these simulation views are often generated for the simulation engines and thus do not appear as readable or understandable by designers. More importantly, these extracted views are generated as a flat view having a single hierarchy that includes all the schematic symbols or models understood by the simulation engine. As a result, an extracted view loses the hierarchical structures of the electronic designs; and the loss of the hierarchical structure further exacerbates the difficulties in understanding or manipulating such an extracted view, even if the extracted view were to be editable.
Another problem with conventional approaches is that the same schematic symbol may correspond to multiple schematic instances in the schematic design and hence multiple layout instances in the layout. During the generation of an extracted view from the layout in conventional approaches, these multiple layout instances may be extracted and represented as the same schematic symbol whereas these multiple layout instances may not necessarily be identically implemented in the layout. For example, two or more of these multiple layout instances may be routed differently although then all correspond to the same schematic symbol. As a result, conventional simulation views cannot correct capture the differences in, for example, parasitics and/or electrical characteristics between these layout instances.
Thus, what are needed are methods, systems, and computer program products for implementing a schematic driven extracted views for various analysis modules or simulation engines in a more efficient and effective manner and to address at least the aforementioned issues and shortcomings.